Process technology advances in integrated circuit fabrication have led to more compact chip designs. Typically, as a process technology scales the physical dimensions of a chip, the associated power supply voltages are reduced as well. This reduction is necessary to prevent damage to devices from signals exceeding physical limitations on voltages and electric fields, and to reduce the overall power consumption. Trends in CMOS power supply scaling have progressed from operating voltages of 5 volts, typical for a 0.35 μm process technology, to 3.3, 2.4, and even 1.8 volts as the feature size has reduced to 90 nm.
Within the interior of the integrated circuit, the reduced operating voltages usually provide benefits in terms of power, thermal dissipation, and other performance attributes. However, the integrated circuit must necessarily be interfaced to other circuits and systems, oftentimes operating with signals at higher voltages. It is a task of the input-output (I/O) buffer circuit to provide this interface. As an example, it may be desirable to interface an integrated circuit which operates from a 2.4 volt power supply to a system having transistor-transistor logic (TTL) compatible inputs operating at nominally 5 volts. Thus, a need exists for an I/O buffer circuit which can tolerate applied voltages exceeding the circuit's power supply voltage. For the purpose of this specification, circuits having the capability of operating on signal voltages which exceed the power supply potential will be termed voltage tolerant. Not only is it desirable for a voltage tolerant buffer circuit to withstand elevated voltages without damage, but also to prevent excessive currents resulting from the applied signals. This is necessary to limit power consumption within the system and to reduce other potentially deleterious effects such as electromagnetic interference (EMI) which can result from excessive current transients.
FIG. 1 shows a schematic diagram of a portion of a voltage tolerant I/O buffer circuit as known in the prior art. An I/O circuit portion 100 is comprised of a PMOS pull-up transistor 102, a passgate 120, PMOS transistors 104, 106, and 108, a PMOS passgate transistor 122, an NMOS transistor 110, and an inverter 130. The I/O circuit portion 100 is coupled to a first power supply potential Vdd, a second power supply potential gnd, and a pad 140. The PMOS pull-up transistor 102 provides means to raise the output voltage on the pad 140 when the circuit is operated in an output mode. The gate of the PMOS pull-up transistor 102 is controlled by a signal p_dc which is propagated through the passgate 120, the passgate 120 being coupled to the gate terminal of the PMOS pull-up transistor 102. When the circuit is operated in an input mode and the potential applied to the pad 140 exceeds the first power supply potential Vdd, the PMOS transistors 104 and 106 begin to conduct, raising the potential on the gate terminal of the PMOS pull-up transistor 102 and an nwell signal potential, respectively. In addition, the PMOS transistor 108 begins to conduct, raising the gate terminal potential of the PMOS passgate transistor 122. Both the nwell signal potential and the gate terminal potential of the passgate transistor 122 will rise above the first power supply potential Vdd, tracking the potential applied to the pad, effectively biasing the PMOS passgate transistor 122 to an off condition. The NMOS transistor 110 provides means for pulling the gate terminal of the PMOS passgate transistor 122 to the second power supply potential gnd. The NMOS transistor 110 is controlled by the inverter 130 which is coupled to the input pad 140. A disadvantage to the configuration of the I/O circuit portion 100 is the existence of a parasitic or “shoot through” current being induced in the inverter 130 when an input potential intermediate between the second power supply potential gnd and first power supply potential Vdd is applied to the pad. This could be especially troublesome if the pad is placed in a tri-state condition by the external system, allowing the pad potential to float at an uncontrolled level. Tri-state conditions are commonly employed on signal lines and data busses as a power-saving measure and to provide an intermediate condition when the line or bus is transitioning from an input to output condition or vice versa. It is evident from FIG. 1 that a means for providing pull-down on the gate terminal of the PMOS passgate transistor 120 without the limitations imposed by inverter 130 is desirable.
FIG. 2 shows a schematic diagram of a well pulling circuit 200 as known in the prior art, from U.S. Pat. No. 6,573,765 B2 to Bales et al. The well pulling circuit is coupled to a first power supply potential Vdd and a second power supply potential GND. Attention is directed to PMOS transistor 226 and PMOS transistor 228 which comprise an FWELL switch circuit 227 for the purpose of controlling the potential of a signal FWELL which is coupled to an output node 210. Column 5, lines 9 through 15 of the '765 specification state: “During the transition between the deactivation/activation of the PMOS transistors 226 and 228, current will flow through the FWELL switch 227. However, it will be appreciated that the dimensions of transistors 226 and 228 should be selected such that large transition currents are minimized, but the output node 210 can still be charged and discharge quickly enough to track a fast transitioning signal.” Column 5, lines 16 through 26 of the '765 specification further describe conditions which bias PMOS transistor 240 to couple node 207 to the input pad, causing a static current in PMOS transistor 206.
FIG. 3, from the '765 patent to Bales et al., shows an output driver circuit 300 for use in conjunction with the well pulling circuit of FIG. 2. The output driver is coupled to a first power supply potential Vdd, a second power supply potential GND, and to the FWELL signal (FIG. 2). Attention is directed to a PMOS balancing transistor 348 which is employed to couple the bulk terminal and the gate terminal of a PMOS pull-up transistor 304. The PMOS balancing transistor 348 comprises the means by which the gate terminal of the PMOS pull-up transistor 304 is raised above the power supply potential. The pull-down function for the output driver is accomplished by means of an NMOS pull-down transistor 310 and an NMOS pull-down transistor 312 which are serially connected to comprise a stacked configuration.
Typical I/O buffer circuits include a PMOS pull-up transistor for the purpose of driving logic high data output signals. The PMOS transistor is attractive as a pull-up device because its current-voltage behavior results in the device exhibiting low series resistance and excellent current drive when used to couple a signal line to a positive power supply potential. A disadvantage to the device is that it is held in the off condition by means of applying a positive potential, typically the power supply potential, to its gate terminal. If a potential exceeding the power supply potential is applied to the drain of the device, it will begin to conduct, providing a current path from the drain to the source. This may disrupt the applied signal level, and in the extreme will induce variations of the power supply potential. What is needed is a circuit design which enables PMOS transistors to be employed as pull-up devices without undesirable conduction paths when the input potential of an I/O buffer circuit exceeds the power supply potential. Furthermore, the circuit should be simple in order to conserve valuable space on the chip and should have well-behaved transition characteristics between its various operating modes, minimizing shoot-through currents, leakage currents, or other current-voltage extremes.